Hybrid Design of Pseudo Random Number Generator Using Shift Register FPGA and CMOS VLSI

Dr. M. Rajasekhar , R.Prathyusha, A.Hemasri, B.Geethanjali, A.Venkata Dhanalakshmi

The proliferation of digital systems in various applications necessitates the development of efficient pseudo-random number generators (PRNGs) for cryptographic and data processing purposes. In this study, we present a novel approach to PRNG design, leveraging a hybrid combination of Shift Register Field-Programmable Gate Arrays (FPGA) and Complementary Metal-Oxide-Semiconductor (CMOS) Very Large-Scale Integration (VLSI) technology. This hybrid design capitalizes on the strengths of both FPGA and CMOS VLSI to achieve enhanced performance and versatility.

The FPGA-based component of the PRNG system offers configurability and parallelism, allowing for rapid and customizable PRNG generation. The CMOS VLSI component, on the other hand, ensures low power consumption and compact integration, ideal for embedded applications. By combining these two technologies, the PRNG achieves a delicate balance between flexibility and efficiency.

We evaluate the hybrid PRNG design through rigorous testing and analysis, including statistical tests, spectral tests, and computational performance assessments. Our results demonstrate that the hybrid PRNG outperforms standalone FPGA or CMOS-based PRNGs in terms of randomness, uniformity, and speed, making it suitable for a wide range of applications in cryptography, secure communications, and data processing.

The hybrid PRNG design presented in this study not only contributes to the advancement of PRNG technology but also offers a versatile solution for engineers and researchers seeking to tailor their PRNG systems to specific application requirements while optimizing performance and energy efficiency.