Difference Set Codes Based Majority Logic Fault Detection

E.Jebamalar Leavline; F. Jabeena; M.Dhivyapriya, V.Kalaiyarasi

Abstract

Errors in memory applications such as SRAM, is increased now a days due to technology scaling, higher package density and lower voltages even at normal terrestrial environments. There are several techniques to detect and correct the errors. These techniques can only detect single error and double errors due to the low encoding and decoding complexity. It leads to longer decoding time and large power consumption. In majority logic decoding technique, different set cyclic codes are used for multierror detection/correction. DSCC is a part of LDPC (Low Density Parity Check) codes. Since this technique is independent of code size.

Keywords

Fault Detection, Difference Set Codes, LDPC, SRAM.

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Cites this article as

[E.Jebamalar Leavline , F. Jabeena , M.Dhivyapriya, V.Kalaiyarasi (2015), Difference Set Codes Based Majority Logic Fault Detection, International Journal of Innovative Research in Engineering & Management (IJIREM), Vol-2, Issue-6, Page No-91-94], (ISSN 2347 - 5552). www.ijirem.org